1. Field of the Invention
The present invention relates to field emission devices (“FEDs”). More specifically, the present invention relates to large-area FED structures and the method of making such structures.
2. Background of the Invention
Currently, in the world of computers and elsewhere, the dominate technology for constructing flat panel displays is liquid crystal display (“LCD”) technology and the current benchmark is active matrix LCDs (“AMLCDs”). The drawbacks of flat panel displays constructed using AMLCD technology are the cost, power consumption, angle of view, smearing of fast moving video images, temperature range of operation, and the environmental concerns of using mercury vapor in the AMLCD's backlight.
A competing technology is cathode ray tube (“CRT”) technology. In this technology area, there have been many attempts in the last 40 years to develop a practical flat CRT. In the development of flat CRTs, there has been the desire to use the advantages provided by the cathodoluminescent process for the generation of light. The point of failure in the development of flat CRTs has centered on the complexities in the developing of a practical electron source and mechanical structure.
In recent years, FED technology has come into favor as a technology for developing low-power, flat panel displays. FED technology has the advantage of using an array of cold cathode emitters and cathodoluminescent phosphors for the efficient conversion of energy from an electron beam into visible light. Part of the desire to use FED technology for the development of flat panel displays is that it is very conducive for producing flat screen displays that will have high performance, utilize low power, and be light weight. Some of the specific recent advances associated with FED technology that have made it a viable alternative for flat panel displays are large-area 1 μm lithography, large-area thin-film processing capability, high tip density for the electron emitting micropoints, a lateral resistive layer, new types of emitter structures and materials, and low-voltage phosphors.
Referring to FIG. 1, a representative cross-section of a prior art FED is shown generally at 100. As is well known, FED technology operates on the principal of cathodoluminescent phosphors being excited by cold cathode field emission electrons. The general structure of a FED includes a silicon substrate or baseplate 102 onto which a thin conductive structure is disposed. Silicon baseplate 102 may be a single crystal silicon layer.
The thin conductive structure may be formed from doped polycrystalline silicon that is deposited on baseplate 102 in a conventional manner. This thin conductive structure serves as the emitter electrode. The thin conductive structure is usually deposited on baseplate 102 in strips that are electrically connected. In FIG. 1, a cross section of emitter electrode strips 104, 106, and 108 is shown. The number of strips for a particular device will depend on the size and desired operation of the FED.
At predetermined sites on the respective emitter electrode strips, spaced-apart patterns of micropoints are formed. In FIG. 1, micropoint 110 is shown on emitter electrode strip 104, micropoints 112, 114, 116, and 118 are shown on emitter electrode strip 106, and micropoint 120 is shown on emitter electrode strip 108. With regard to the patterns of micropoints, on emitter electrode strip 106, a square pattern of 16 micropoints, which includes micropoints 112, 114, 116, and 118, may be positioned at that location. However, it is understood that one or a pattern of more than one micropoint may be located at any one site. The micropoints also may be randomly placed rather than being in any particular pattern.
Preferably, each micropoint resembles an inverted cone. The forming and sharpening of each micropoint is carried out in a conventional manner. The micropoints may be constructed of a number of materials, such as silicon or molybdenum, for example. Moreover, to ensure the optimal performance of the micropoints, the tips of the micropoints can be coated or treated with a low-work function material.
Alternatively, the structure substrate, emitter electrode, and micropoints may be formed in the following manner. The single crystal silicon substrate may be made from a P-type or an N-type material. The substrate may then be treated by conventional methods to form a series of elongated, parallel extending strips in the substrate. The strips are actually wells of a conductivity type opposite that of the substrate. As such, if the substrate is P-type, the wells will be N-type and vice-versa. The wells are electrically connected and form the emitter electrode for the FED. Each conductivity well will have a predetermined width and depth (which it is driven into the substrate). The number and spacing of the strips are determined to meet the desired size of field emission cathode sites to be formed on the substrate. The wells will be the sites over which the micropoints will be formed. No matter which of the two methods of forming the strips is used, the resulting parallel conductive strips serve as the emitter electrode and form the columns of the matrix structure.
After either of two methods of forming the emitter electrode is used, insulating layer 122 is deposited over emitter electrode strips 104, 106, and 108, and the pattern micropoints located at predetermined sites on the strips. The insulating layer 122 may be made from a dielectric material such as silicon dioxide (SiO2).
A conductive layer is disposed over insulating layer 122. This conductive layer forms extraction structure 132. The extraction structure 132 is a low-potential electrode that is used to extract electrons from the micropoints. Extraction structure 132 may be made from chromium, molybdenum, or doped polysilicon, amorphous silicon, or silicided polysilicon. Extraction structure 132 may be formed as a continuous layer or as parallel strips: If parallel strips form extraction structure 132, it is referred to as an extraction grid, and the strips are disposed perpendicular to emitter electrode strips 104, 106, and 108. The strips, when used to form extraction structure 132, are the rows of the matrix structure. Whether a continuous layer or strips are used, once either is positioned on the insulating layer 122, they are appropriately etched by conventional methods to surround but be spaced away from the micropoints.
At each intersection of the extraction and emitter electrode strips or at desired locations along emitter electrode strips, when a continuous extraction structure is used, a micropoint or pattern of micropoints are disposed on the emitter strip. Each micropoint or pattern of micropoints is meant to illuminate one pixel of the screen display.
Once the lower portion of the FED is formed according to either of the methods described above, faceplate 140 is fixed in a predetermined distance above the top surface of the extraction structure 132. Typically, this distance is several hundred μm. This distance may be maintained by spacers 136 and 138 that are formed by conventional methods and have the following characteristics: (1) non-conductive or highly resistive to prevent an electrical breakdown between the anode (at faceplate 140) and cathode (at emitter electrode strips 104, 106, and 108), (2) mechanically strong and slow to deform, (3) stable under electron bombardment (low secondary emission yield), (4) capable of withstanding the high bakeout temperatures in the order of 500° C., and (5) small enough not to interfere with the operation of the FED. Representative spacers 136 and 138 are shown in FIG. 1.
Faceplate 140 is a cathodoluminescent screen that is constructed from clear glass or other suitable material. A conductive material, such as indium tin oxide (“ITO”), is disposed on the surface of the glass facing the extraction structure 132. ITO layer 142 serves as the anode of the FED. A high vacuum is maintained in area 134 between faceplate 140 and baseplate 102.
Black matrix 149 is disposed on the surface of the ITO layer 142 facing extraction structure 132. Black matrix 149 defines the discrete pixel areas for the screen display of the FED. Phosphor material is disposed on ITO layer 142 in the appropriate areas defined by black matrix 149. Representative phosphor material areas that define pixels are shown at 144, 146, and 148. Pixels 144, 146, and 148 are aligned with the openings in extraction structure 132 so that a micropoint or groups of micropoints that are meant to excite phosphor material are aligned with that pixel. Zinc oxide is a suitable material for the phosphor material, since it can be excited by low energy electrons.
A FED has one or more voltage sources that maintain emitter electrode strips 104, 106, and 108, extraction structure 132, and ITO layer 142 at three different potentials for proper operation of the FED. Emitter electrode strips 104, 106, and 108 are at “−” potential, extraction structure 132 is at a “+” potential, and the ITO layer 142 is at a “++” potential. When such an electrical relationship is used, extraction structure 132 will pull an electron emission stream from micropoints 110, 112, 114, 116, 118, and 120, and, thereafter, ITO layer 142 will attract the freed electrons.
The electron emission streams that emanate from the tips of the micropoints fan out conically from their respective tips. Some of the electrons strike the phosphors at 90° to the faceplate, while others strike it at various acute angles.
The basic structure of the FED just described generally will not include spacers when the diagonal screen size is less than 5 inches. When the screen size is greater than 5 inches, spacers are needed to maintain the correct separation between the emitter electrode and the faceplate under the force of atmospheric pressure on the FED. As the FED devices increase in size, the need for spacers increases so this separation is properly maintained. An alternative to the use of spacers is the use of thick glass. However, this thick glass is heavy and expensive.
In the fabrication of small-area FED structures with diagonal screen sizes between 1–5 inches, there is little difficulty in achieving substantial uniformity in the thickness of the insulating and conductive layers that are disposed on the substrate, or in forming substantially uniform micropoints on the emitter electrodes in openings in the insulating and conductive layers. Conventional deposition and etching techniques have been used for such fabrication. This also has been generally true with regard to FEDs with diagonal screen sizes up to approximately 8 inches. However, as the diagonal screen sizes of FEDs increase beyond 8 inches, there has been considerable difficulty in forming uniform micropoints by the Spindt process which will be discussed subsequently.
There are a variety of reasons why the above problems and difficulties exist, and the desired design goals have not been reached for large-area FEDs. Most of the reasons are that the fabrication techniques which permit the production of small-area FEDs fail miserably when a large number of openings need to be etched and aligned with micropoints, and when there are a large number of micropoints to be formed. Another reason is that the micropoints are not formed so that they have the proper properties needed to permit the production of high-quality, high-resolution images in large-area FEDs. A further reason is the high cost of fabrication if current technology is used. A yet further reason is the improper structure and placement of spacers in large-area FEDs. These problems exist whether a large-area FED is monochrome, 256 gray scale, or color.
Attempts to fabricate a lower FED structure (which includes the substrate, insulating and conductive layers, and micropoints) with the requisite uniformity in structure and performance have relied on a number of prior process methods. The process that is believed the best is the Spindt process, which was developed in the mid-1960s. This process has been attempted to be used for fabricating large-area FEDs for the formation of micropoint structures for producing high-quality, high-resolution images. This process uses a directional molybdenum evaporation process that calls for depositing a thin molybdenum film on the surface of the conductive layer that is over the insulating layer. Preferably, this film has a thickness that is greater than the diameter of the openings that are made in the conductive and insulating layers. According to the molybdenum process, the openings in the conductive and insulating layers are closed with the molybdenum, and then the micropoints are formed in the openings from the deposited molybdenum. That is, the micropoints are formed by removing unwanted molybdenum material from the surface of the conductive layer and within the cavity by conventional processing steps. This, hopefully, would leave substantially uniform molybdenum cones on the substrates that are aligned with the openings in the conductive and insulating layers. This whole process, however, depends on the uniformity in the thin-film layer that is deposited and the accuracy of the etching process. As has been the case, however, this process is adequate for small-area FEDs but wholly inadequate for large-area FEDs because of a lack of uniformity in micropoint formation over the large-area and the high percentage of misalignments.
As the diagonal screen size of FEDs increases beyond 10 inches, there are distinct problems with current technology in producing FEDs with high-quality, high-resolution images. Moreover, there are also problems in overcoming the resistor/capacitor (“R/C”) times for the large-area FEDs to operate efficiently. This is because it will take a relatively long period of time to charge the large capacitor formed by the emitter electrode, and the extraction structure.
Another problem with current technology is the spacers that are to be used for large-area FEDs. As the screen displays increase above 10 inches, there can be difficultly in maintaining the proper distance between the faceplate and emitter electrode. To overcome this problem, there is a desire to space the faceplate and emitter electrode farther apart and then use increased anode voltages in the range of 2–6 kV rather the lower voltages that are desired. In such devices, large-diameter spacers are used to maintain the spacing.
An alternative has been to consider the use of clear glass spheres. This was thought to permit the use of lower anode voltages and smaller distances between the faceplate and emitter electrode. However, the use of these spheres has had a detrimental effect on the resolution of the FED because of the base-to-height ratio of the glass spheres. When large glass spheres are used, some of the electrons emitted from the micropoints will contact the spheres rather than the phosphor pixel elements. This means that a number of electrons will not be used to produce the portion of the image they were meant to produce. The use of glass spheres also limits the amount of the anode voltage that can be used. Moreover, when glass spheres are used and low anode voltages are applied, the power consumption of the FED goes up dramatically, which is highly undesirable. On the other hand, if high-anode voltages are used with glass spheres present, the spheres will breakdown.
Another proposed spacer for use in large-area FEDs has been long paper-thin spacers. These spacers are 250–500 μm high and 30–50 μm thick. Such spacers would run along the whole length of the narrowest sides of the FED. These spacers are made from ceramic strips and are considerably flimsy. As can be readily understood, the larger the diagonal size of the screen display of the FED, the less likely the ceramic-strip spacers will be able to be used to mount and align the emitter electrode and faceplate, or to maintain separation of the anode and cathode under a high vacuum.
There is a desire to provide a structure that will permit the large-area FEDs to be built to operate efficiently. The large-area FEDs that are desired to be built with such a structure are those with a diagonal screen size of 10 inches, or larger.